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Simulation mismatches between RTL and Synthezied netlist - 1

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Tessent Flows

Tessent DFT Solutions: Tessent MemoryBIST -                 Progarmmable, Self-Repair    Tessent DefectSim      -                 AMS defect simulation Tessent LogicBIST     -                 Hybrid TK/LBIST, Test points, OCC Tessent MissionMode  -                In-System Test Tessent BoundaryScan -               1149.1, 1149.6, Contact I/O, Leakage Tests Tessent IJTAG -                            Integration and Verification of IJTAG network and compliant IP Tessent TestKompress -                Compression, hierarchial ATPG Tessent ATPG -                        ...

STIL - Standard Test Interface Langauge

Purpose:  To support various interfacing needs for test generation tools (ATPG tools) and test equipments (ATE)   S tandard T est I nterface L anguage (STIL) Standardised as  IEEE 1450 Provides data exchange between EDA tools from different vendors and ATE interfaces STIL is an open source language  STIL file Contents:  Fig 1. Top level of STIL data model [1] STIL -  Defines the version of STIL present in the file.  This is the first statement of any STIL file, including files opened from the Include statement. Header - Contains general information about the STIL file being parsed.  This block is optional; if present, it shall be the first statement after the STIL statement in the file. Signals - Defines all primary signals under test. SignalGroups - Defines collections of Signals.  Requires reference to use if domain_name is used. ScanStructures - Defines internal scan chain information.  The ScanStructures block or blocks are...

Circuit synthesis with Yosys

Design: LFSR RTL code:  module lfsr (     input  logic        clk,     input  logic        rst_n,  // Active low reset     output logic [3:0]  q );     // Next state logic using XOR feedback     // Polynomial: x^4 + x^3 + 1     always_ff @(posedge clk or negedge rst_n) begin         if (!rst_n) begin             q <= 4'b0001;  // Non-zero initial state         end else begin             // Shift right and feed back XOR of tap points             q <= {(q[2] ^ q[0]), q[3], q[2], q[1]};         end     end endmodule Testbench: // Code your testbench here // or browse Examples module lfsr_tb();     logic       clk;     logic       rst_n; ...

SimpleProcessor: Insertion of JTAG Macro

 SimpleProcessor - Verilog code