Simulation mismatches between RTL and Synthezied netlist - 1

Sensitivity List

1. Synthesis tools infer combinational or latching logic from an always block with a sensitivity list that does not contain the Verilog keywords posedge or negedge.

2. Extra signal in sensitivity list increases the need for compute resources

3. The synthesized logic described by the equations in an always block will always be

implemented as if the sensitivity list were complete.

4. If there any signal missing in sensitivity list those signals won't trigger the execution of a block of code

5. If there are no signals in sensitivity list, the code may run infintely if not caught by tool


 code: https://edaplayground.com/x/QaGF

output1:
# KERNEL: ASDB file was created in location /home/runner/dataset.asdb
# KERNEL: Time: 0 | a: 0, b: 0 | Pre-Synth_1 y: 0,Pre-Synth_2 y: 0, Post-Synth y: 0
# KERNEL: Time: 10 | a: 0, b: 1 | Pre-Synth_1 y: 0,Pre-Synth_2 y: 0, Post-Synth y: 0
# KERNEL: Time: 20 | a: 1, b: 0 | Pre-Synth_1 y: 0,Pre-Synth_2 y: 0, Post-Synth y: 0
# KERNEL: Time: 30 | a: 1, b: 1 | Pre-Synth_1 y: 1,Pre-Synth_2 y: 0, Post-Synth y: 1

output2:
[2025-01-22 08:52:19 UTC] vlib work && vlog '-timescale' '1ns/1ns' design.sv testbench.sv && vsim -c -do "vsim +access+r; run -all; exit"
VSIMSA: Configuration file changed: `/home/runner/library.cfg'
ALIB: Library "work" attached.
work = /home/runner/work/work.lib
WARNING VCP2661 "Infinite loop is possible in ALWAYS statement." "design.sv" 44 3
ERROR VCP2000 "Syntax error. Unexpected token: y_post[_IDENTIFIER]." "testbench.sv" 13 54
FAILURE "Compile failure 1 Errors 1 Warnings Analysis time: 0[s]."
Exit code expected: 0, received: 255