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Circuit synthesis with Yosys

Design: LFSR


RTL code: 

module lfsr (
    input  logic        clk,
    input  logic        rst_n,  // Active low reset
    output logic [3:0]  q
);

    // Next state logic using XOR feedback
    // Polynomial: x^4 + x^3 + 1
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            q <= 4'b0001;  // Non-zero initial state
        end else begin
            // Shift right and feed back XOR of tap points
            q <= {(q[2] ^ q[0]), q[3], q[2], q[1]};
        end
    end

endmodule

Testbench:

// Code your testbench here
// or browse Examples
module lfsr_tb();
    logic       clk;
    logic       rst_n;
    logic [3:0] q;

    lfsr dut (
        .clk(clk),
        .rst_n(rst_n),
        .q(q)
    );

    initial begin
        clk = 0;
        forever #5 clk = ~clk;
    end

    initial begin
        $dumpfile("lfsr_tb.vcd");
        $dumpvars(0, lfsr_tb);

        rst_n = 1'b0;

        #20 rst_n = 1'b1;

        for (int i = 0; i < 20; i++) begin
            @(posedge clk);
            $display("Time=%0t rst_n=%0b q=%b", $time, rst_n, q);
        end

        rst_n = 1'b0;
        #10 rst_n = 1'b1;

        for (int i = 0; i < 5; i++) begin
            @(posedge clk);
            $display("Time=%0t rst_n=%0b q=%b", $time, rst_n, q);
        end

        #10 $finish;
    end

endmodule

Synthesis Script: run.ys

# read design
read -sv design.sv

# elaborate design hierarchy
hierarchy -top full_adder_32bit

# the high-level stuff
proc; opt; fsm; opt; memory; opt
# proc; Converts behavioral code into basic RTL structures
# fsm; Performs state encoding optimization
# memory; Transforms memory arrays into flip-flops or memory blocks
# opt; 


# mapping to internal cell library
# techmap; opt

# mapping flip-flops to cmos_cells.lib
# dfflibmap -liberty cmos_cells.lib

# mapping logic to cmos_cells.lib
# abc -liberty cmos_cells.lib
# show -format png -prefix post_opt
# cleanup
clean

# write synthesized design
write_verilog synth.v

Results

EDA playground netlist output: synth.v

/* Generated by Yosys 0.38+113 (git sha1 91fbd5898, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os) */

(* hdlname = "lfsr" *)
(* top =  1  *)
(* src = "design.sv:2.1-19.10" *)
module lfsr(clk, rst_n, q);
  (* src = "design.sv:10.5-17.8" *)
  wire [3:0] _0_;
  (* src = "design.sv:3.25-3.28" *)
  input clk;
  wire clk;
  (* src = "design.sv:5.25-5.26" *)
  output [3:0] q;
  reg [3:0] q;
  (* src = "design.sv:4.25-4.30" *)
  input rst_n;
  wire rst_n;
  (* \always_ff  = 32'd1 *)
  (* src = "design.sv:10.5-17.8" *)
  always @(posedge clk, negedge rst_n)
    if (!rst_n) q <= 4'h1;
    else q <= { _0_[3], q[3:1] };
  assign _0_[3] = q[2] ^ (* src = "design.sv:15.20-15.31" *) q[0];
  assign _0_[2:0] = q[3:1];
endmodule


EDA playground
fig 1. EDA playground Design and Testbench

fig 2. EDAPlayground logs


fig 3. Netlist




On Ubuntu

fig 4. yosys run.ys

fig 5. xdg-open post_opt.png

Netlist synthesised:

/* Generated by Yosys 0.48 (git sha1 aaa534749, g++ 11.4.0-1ubuntu1~22.04 -fPIC -O3) */

(* hdlname = "lfsr" *)
(* top =  1  *)
(* src = "design.sv:1.1-18.10" *)
module lfsr(clk, rst_n, q);
  (* src = "design.sv:9.5-16.8" *)
  wire [3:0] _0_;
  (* src = "design.sv:2.25-2.28" *)
  input clk;
  wire clk;
  (* src = "design.sv:4.25-4.26" *)
  output [3:0] q;
  reg [3:0] q;
  (* src = "design.sv:3.25-3.30" *)
  input rst_n;
  wire rst_n;
  (* \always_ff  = 32'd1 *)
  (* src = "design.sv:9.5-16.8" *)
  always @(posedge clk, negedge rst_n)
    if (!rst_n) q <= 4'h1;
    else q <= { _0_[3], q[3:1] };
  assign _0_[3] = q[2] ^ (* src = "design.sv:14.20-14.31" *) q[0];
  assign _0_[2:0] = q[3:1];
endmodule








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