SimpleProcessor: Insertion of JTAG Macro

 SimpleProcessor - Verilog code

module SimpleProcessor(
    input wire clk,
    input wire reset,
    input wire [3:0] opcode,  // Operation Code
    input wire [7:0] operand1,
    input wire [7:0] operand2,
    output reg [7:0] result,
    output reg [3:0] status  // Status flags: [3] Zero, [2] Carry, [1] Overflow, [0] Negative
);

    // Register file
    reg [7:0] regA, regB;

    // ALU operations
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            regA <= 8'b0;
            regB <= 8'b0;
            result <= 8'b0;
            status <= 4'b0;
        end else begin
            regA <= operand1;
            regB <= operand2;
            case (opcode)
                4'b0000: result <= regA + regB;  // Addition
                4'b0001: result <= regA - regB;  // Subtraction
                4'b0010: result <= regA & regB;  // AND
                4'b0011: result <= regA | regB;  // OR
                default: result <= 8'b0;         // Default to 0
            endcase

            // Update status flags
            status[3] <= (result == 8'b0);        // Zero flag
            status[2] <= (regA + regB > 8'hFF);   // Carry flag (for addition)
            status[1] <= (~regA[7] & ~regB[7] & result[7]) | (regA[7] & regB[7] & ~result[7]); // Overflow flag
            status[0] <= result[7];               // Negative flag
        end
    end

endmodule

Genus Synthesis and JTAG Macro Insertion script

set_attribute init_hdl_search_path { /home/ganesh/sanket/SimpleProcessor }

# verilog search path

set_attribute init_lib_search_path { /home/ganesh/sanket/LIBS/timing }
# lib files path

set_attribute library { /home/ganesh/sanket/LIBS/timing/slow.lib 
 /home/ganesh/sanket/LIBS/timing/typical.lib 
 /home/ganesh/sanket/LIBS/timing/fast.lib }

read_hdl SimpleProcessor.v
# read design
# read_netlist Netlist.v

set_att hdl_track_filename_row_col true /
# to cross-probe in gui

elaborate

check_dft_rules

gui_show

syn_generic
syn_map
# here
syn_opt

define_dft jtag_instruction_register -name INSTR_REGISTER -length 2
define_dft jtag_instruction -name BYPASS -opcode 11
define_dft jtag_instruction -name EXTEST -opcode 10
define_dft jtag_instruction -name SAMPLE -opcode 01
define_dft jtag_instruction -name PRELOAD -opcode 01

insert_dft jtag_macro \
    -insert_without_pad_logic \
    -create_ports

gui_show