Tessent Flows

Tessent DFT Solutions:

1. Tessent MemoryBIST -                 Progarmmable, Self-Repair   
2. Tessent DefectSim      -                 AMS defect simulation
3. Tessent LogicBIST     -                 Hybrid TK/LBIST, Test points, OCC
4. Tessent MissionMode  -                In-System Test
5. Tessent BoundaryScan -               1149.1, 1149.6, Contact I/O, Leakage Tests
6. Tessent IJTAG -                            Integration and Verification of IJTAG network and compliant IP
7. Tessent TestKompress -                Compression, hierarchial ATPG
8. Tessent ATPG -                             Automatic Test Pattern Generation

Source: https://www.youtube.com/watch?v=h-Erql1g5yY

Tessent Scan Chain Insertion

set_context dft –scan -design_id gate

# set context for tessent shell

read_cell_library ../library/tessent/*.lib

#  Loads the technology cell library containing scan cell definitions and other standard cells.

read_verilog synthesized_netlist.v

# Read design files that needs scan chain insertion

set_tsdb_output_directory ../tsdb_rtl

# Specifies where Tessent will store its database files and outputs.

read_design cpu_top -design_id rtl2 -no_hdl

set_current_design cpu_top

# Set current design as cpu_top

check_design_rules

#  Check rules

#  TODO: Fix violations

#  Tessent Shell transitions from Setup mode to Analysis mode.

set edt_instance [get_name_list [get_instance -of_module \

                           [get_name [get_icl_module -filter \

                            tessent_instrument_type==mentor::edt]]]]

add_scan_mode edt_mode -edt_instance $edt_instance

# Identifies EDT (Embedded Deterministic Test) instances &

# Configures the scan mode accordingly.

analyze_scan_chains

report_scan_chains

# Analyzes the design to determine optimal scan chain configurations 

# Generates a report of the proposed scan chains.

insert_test_logic
# Performs the actual scan chain insertion, converting regular flip-flops to scan cells 

# Also connecting them into chains.

exit

# Exits tessent shell

Why Hierarchical DFT? 

Hierarchical DFT has several advantages:

• Parallelization of task of each block/partition.
• Reduced compute to perform the given task.
• Faster pattern generation and simulation run times.
• DFT performed earlier at block level and out of design critical path.

Tessent MemoryBIST flow:

Source: https://www.youtube.com/watch?v=W-jlBiecKfU&list=PLarNRyV2uFZgsmierg-lUtTmcuc_6YQlQ&index=10

fig 1. Tessent MemoryBIST flow

set_context dft -rtl

# Sets up the DFT (Design for Test) context and runtime environment

# Setup >

read_cell_library ../techlib_odk_tnt.local/4.1/tennen1/sdk.tcolllib

#  Loads the technology cell library containing standard cells and memory definitions

set_design_sources -format verilog -r {../data/design/mem ../data/design/rtl} -system read_verilog ../data/rtl/block8.v

#  Specifies input Verilog design files

set_current_design block

# Reads the main design Verilog file for block

set_design_level sub_block

# Specifies this is a sub-block level design

set_dft_specification_requirements -memory_test on

# Enables memory testing requirements for MBIST

# help set_dft_specification_requirements

add_clock CLK -period 12ns -label clks

# Defines the test clock with a 12ns period

check_design_rules

# Verifies the design meets MBIST insertion rules

# Setup > to Analysis >

create_dft_specification

# Creates the DFT specification for memory testing

report_config_data DftSpecification[block.rtl]

# Generates a report of the MBIST configuration

display_specification

# Shows the current MBIST specification in GUI Mode

process_dft_specification

# Processes the DFT specification by validating of IP in IP generation phase prepares for MBIST insertion

# Analysis > to Insertion >

extract_icl

# create ICL file for this block

create_pattern_specification

# ICL elaboration and checking and Generate patterns for instruments

process_pattern_specification

# writes patterns and simulation directory

run_testbench_simulations

check_testbench_simulations

# Runs and check testbench simlution

Tessent ATPG

Stuck at faults

Source: https://www.youtube.com/watch?v=j0AYw-NDX_g&t=1933s

set_context patterns -scan    

# Initializes the pattern generation context

read_verilog scan-inserted.v -force    

# Reads the scan-inserted netlist

read cell library tcbn65gplushpbwp.mdt    

# Loads the 65nm technology library

set_current_design

dofile scan1.spf.do    

# Loads scan protocol/configuration file

set_system_mode analysis    

# Sets the tool to analysis mode

set_fault_type stuck    

# Specifies stuck-at fault model

add_faults -all         

# Adds all possible stuck-at faults

create_patterns        

# Generates the test patterns

# Generating patterns in different formats:

write_patterns serialpatterns_stuck.v -verilog -serial -replace    # Serial patterns

write_patterns parallelpatterns_stuck.v -verilog -parallel -replace    # Parallel patterns

write_patterns pattern_stuck.ascii -ascii -parallel -replace    # ASCII format

Transisition

set_context patterns -scan    

# Initializes pattern context

read_verilog scan-inserted.v -force    

# Reads scan-inserted netlist

read cell library tcbn65gplushpbwp.mdt    

# Loads 65nm library

set_current_design

dofile scan1.spf.do    # Loads scan protocol file

set_output_masks off          

# Disables output masking

set transition holdpi on      

# Enables hold of primary inputs during transition

set_system_mode analysis      

# Sets analysis mode

set_fault_type transition     

# Specifies transition fault model instead of stuck-at

add_faults -all              

# Adds all possible transition faults

create_patterns              

# Generates patterns

# Writing patterns in different formats:

write_patterns serialpatterns.v -verilog -serial -replace

write_patterns parallelpatterns.v -verilog -parallel -replace

write_patterns pattern.ascii -ascii -parallel -replace